NBBITS=_8_BIT, WDRBT=DISABLED, SMM=SPI, CSMODE=NOT_RELOADED, LLB=DISABLED
Mode Register
| SMM | Serial Memory Mode 0 (SPI): The QSPI is in SPI mode. 1 (MEMORY): The QSPI is in Serial Memory mode. |
| LLB | Local Loopback Enable 0 (DISABLED): Local loopback path disabled. 1 (ENABLED): Local loopback path enabled. |
| WDRBT | Wait Data Read Before Transfer 0 (DISABLED): No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. 1 (ENABLED): In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. |
| CSMODE | Chip Select Mode 0 (NOT_RELOADED): The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. 1 (LASTXFER): The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. 2 (SYSTEMATICALLY): The chip select is deasserted systematically after each transfer. |
| NBBITS | Number Of Bits Per Transfer 0 (_8_BIT): 8 bits for transfer 8 (_16_BIT): 16 bits for transfer |
| DLYBCT | Delay Between Consecutive Transfers |
| DLYCS | Minimum Inactive QCS Delay |